general description the max4895e integrates level-translating buffers and features r, g, b port protection for vga signals. the max4895e has h, v (horizontal, vertical) translat- ing buffers that take low-level cmos inputs from the graphics outputs to meet full +5.0v, ttl-compatible outputs. each output can drive ?0ma and meet the vesa specification. in addition, the device takes the +5.0v, direct digital control (ddc) signals and trans- lates them to the lower level required by the graphics device. this level is set by the user by connecting v l to the graphics output supply. the r, g, b terminals pro- tect the graphics output pins against electrostatic dis- charge (esd) events. all seven outputs have high-level esd protection. the max4895e is specified over the extended -40? to +85? temperature range, and is available in a 16-pin, 3mm x 3mm tqfn package. applications notebook computers desktops servers graphics cards features ? esd protection on h1, v1, sda1, scl1, r, g, and b ?5kv?uman body model ?kv?ec 61000-4-2, contact discharge ? low quiescent current, i q 5? (max) ? low 3pf (max) capacitance (r, g, b ports) ? ddc level-shifting protection and isolation ? horizontal sync, vertical sync level shifting/ buffering ? input compatible with v l ? output full +5.0v ttl compatible (per vesa) ? ?0ma drive on each h, v terminal ? space-saving, lead-free, 16-pin (3mm x 3mm) tqfn package max4895e vga port protector ________________________________________________________________ maxim integrated products 1 ordering information max4895e 1 f gnd +5v v cc 1 f +3.3v v l en b g r sda0, scl0 h0, v0 2 2 2 2 vga outputs vga port sda1, scl1 h1, v1 n.c. typical operating circuit 19-4569; rev 1; 6/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX4895EETE+ -40c to +85c 16 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. vesa is a registered service mark of video electronics standards association corporation.
max4895e vga port protector 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +4.5v to +5.5v, v l = +2.0v to v cc , t a = t min to t max , unless otherwise noted. typical values are at v cc = +5.0v, v l = +3.3v, and t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . (all voltages referenced to gnd.) v cc ........................................................................-0.3v to +6.0v v l .............................................................-0.3v to +(v cc + 0.3v) r, g, b, h1, v1, scl1, sda1...................-0.3v to +(v cc + 0.3v) en, h0, v0, scl0, sda0 ............................-0.3v to +(v l + 0.3v) continuous current through sda_, scl_.........................?0ma continuous short-circuit current h1, v1..........................?0ma continuous power dissipation (t a = +70?) for multilayer board: 16-pin tqfn (derate 20.8mw/? above +70?) .......1667mw junction-to-case thermal resistance ( jc ) (note 1) ......7?/w junction-to-ambient thermal resistance ( ja ) (note 1) ........................................................................48?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units supply operation supply voltage v cc 4.5 5.5 v logic supply voltage v l v l v cc 2 3.3 5.5 v v cc supply current i cc v h0 , v v0 = 0v, v en = v l 0.5 5.0 a v l supply current i l v h0 , v v0 = 0v, v en = v l (no load) 0.5 5.0 a rgb channels r, g, b capacitance c out f = 1mhz, v r,g,b = 1v p-p (note 3) 2.2 pf r, g, b leakage v cc = +5.5v -1 +1 a h_, v_, en channels input threshold low v il v l = +3.0v 0.8 v input threshold high v ih v l = +3.6v 2.0 v input hysteresis v hyst 100 mv input leakage current i leak v l = +3.3v, v cc = +5.5v -1 +1 a output-voltage low v ol i out = 10ma sink, v cc = +4.5v 0.8 v output-voltage high v oh i out = 10ma source, v cc = +4.5v 2.4 v propagation dela y t pd r l = 2.2k , c l = 10pf, v ol = +0.8v, v oh = +2.4v 15 ns enable time t on , t off 15 ns sda_, scl_ (ddc) channels on-resistance, sda, scl r on v cc = +5.5v, i sda, scl = 10ma, v sda, scl = +0.5v 20 55 leakage current, sda, scl i leak v l = 0v -1 +1 a
max4895e vga port protector _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +4.5v to +5.5v, v l = +2.0v to v cc , t a = t min to t max , unless otherwise noted. typical values are at v cc = +5.0v, v l = +3.3v, and t a = +25?.) (note 2) parameter symbol conditions min typ max units esd protection sda1, scl1, h1, v1, r, g, b human body model (note 4) 15 kv sda1, scl1, h1, v1, r, g, b iec 61000-4-2 contact 8 kv note 2: all devices are 100% production tested at t a = +25?. all temperature limits are guaranteed by design. note 3: guaranteed by design, not production tested. note 4: tested terminals to gnd; 1? bypass capacitors on v cc and v l . r on vs. v sda0 max4895e toc01 v sda0 (v) r on ( ) 2.0 1.5 1.0 3.0 2.5 4.0 0.5 3.5 15 30 45 60 0 0 4.5 t a = -40 c t a = +25 c t a = +85 c v l = +5v t a = -40 c t a = +25 c t a = +85 c v l = +3.3v sda0, scl0 are interchangeable hv buffer output-voltage high vs. temperature max4895e toc02 temperature ( c) output voltage (v) 10 -15 35 60 4.5 5.0 5.5 6.0 4.0 -40 85 i out = 8ma hv buffer output-voltage low vs. temperature max4895e toc03 temperature ( c) output voltage (v) 10 -15 35 60 0.4 0.2 0.6 0.8 1.0 0 -40 85 i out = 8ma typical operating characteristics (v cc = +5.0v, v l = +3.3v, and t a = +25?, unless otherwise noted.)
max4895e vga port protector 4 _______________________________________________________________________________________ pin description pin name function 1 r high-esd protection diodes for rgb signals 2 g high-esd protection diodes for rgb signals 3 b high-esd protection diodes for rgb signals 4 gnd ground 5 v l supply voltage, +2.0v to v cc . bypass v l to gnd with a 1f ceramic capacitor. 6 n.c. no connection. leave unconnected. 7 sda0 sda i/o. sda0 referenced to v l . 8 sda1 sda i/o. sda1 referenced to v cc . 9 scl0 scl i/o. scl0 referenced to v l . 10 scl1 scl i/o. scl1 referenced to v cc . 11 h0 horizontal sync input 12 h1 horizontal sync output 13 v0 vertical sync input 14 v1 vertical sync output 15 v cc power-supply voltage, +4.5v to +5.5v. bypass v cc to gnd with a 1f ceramic capacitor. 16 en enable for h1 and v1 outputs ep exposed pad. connect ep to gnd or leave unconnected. for enhanced thermal dissipation, connect ep to a copper area as large as possible. do not use ep as a sole ground connection. 15 16 14 13 5 6 7 b gnd 8 r scl1 scl0 h1 13 v1 4 12 10 9 v cc en sda1 sda0 n.c. v l max4895e gh0 2 11 v0 tqfn (3mm top view ep pin configuration
max4895e vga port protector _______________________________________________________________________________________ 5 applications information the max4895e provides the level shifting necessary to drive two standard vga ports from a graphics controller as low as +2.2v. internal buffers drive the hsync and vsync signals to vga standard ttl levels. the ddc switch provides level shifting by clamping signals to a diode drop less than v l (see the typical operating circuit ). connect v l to +3.3v for normal operation. power-supply decoupling bypass v cc and v l to ground with a 1? ceramic capacitor as close as possible to the device. pcb layout high-speed switches such as the max4895e require proper pcb layout for optimum performance. ensure that impedance-controlled pcb traces for high-speed signals are matched in length and are as short as pos- sible. connect the exposed pad to a solid ground plane. functional diagram max4895e 15kv 15kv 15kv h1 v1 h0 v0 en scl0 sda1 scl1 sda0 clamp 15kv 15kv b 15kv g 15kv r v l v cc gnd
max4895e vga port protector 6 _______________________________________________________________________________________ detailed description the max4895e integrates level-translating buffers and features r, g, b port protection for vga signals. horizontal and vertical synchronization (h0/v0) inputs feature level-shifting buffers to support low-voltage cmos or standard ttl-compatible graphics con- trollers. the device meets ?0ma vesa drive require- ments. the max4895e also features i 2 c level shifting using two nmos devices. all outputs maintain ?5kv human body model (hbm) and ?kv contact discharge per iec 61000-4-2 on seven terminals (sda1, scl1, h1, v1, r, g, b). the r, g, b pads pro- tect the digital-to-analog converter (dac) and are sim- ply placed in parallel with the r, g, b outputs for the dac and vga socket. horizontal/vertical sync level shifter hsync/vsync are buffered to provide level shifting and drive capability to meet the vesa specification. input logic levels (v il , v ih ) are connected to v l (see the electrical characteristics table). the level-shifted outputs (h1 and v1) are pulled low when en is driven low (see table 1). logic-level output (v ol , v oh ) are +5.0v ttl compatible. display data channel switches the max4895e incorporates two nmos switches for i 2 c level shifting. the sda, scl terminals are voltage clamped to a diode drop less than the v l voltage. voltage clamping provides protection and compatibility with sda, scl signals and low-voltage asics. supply +2.5v to +3.3v on v l to provide voltage clamping for vesa i 2 c-compatible signals. the sda, scl switches are identical, and each switch can be used to route sda or scl signals. rgb there are three terminals for r, g, and b. the only function of these terminals is to provide high-level esd protection to the rgb lines, while at the same time, keeping the capacitance on the rgb lines to a mini- mum. the r, g, b terminals are identical, and any of the three terminals can be used to protect red, green, or blue video signals. esd protection as with all maxim devices, esd-protection structures are incorporated on all terminals to protect against electrostatic discharges encountered during handling and assembly. additionally, the max4895e is protected to ?5kv on the rgb terminals and outputs h1, v1, sda1, and scl1 by the human body model (hbm). for optimum esd performance, bypass v cc to ground with a 1? ceramic capacitor. esd protection can be tested in various ways. the r, g, b terminals and outputs h1, v1, sda1, and scl1 of the max4895e are characterized for protection to the following limits: ??5kv using the human body model ??kv iec 61000-4-2 contact discharge esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report documenting test setup, methodology, and results. table 1. hv truth table en function 1 hsync/vsync level shifting enabled 0 h1, v1 = 0 table 2. ddc truth table en function 1 sda0 to sda1 scl0 to scl1 0 sda1, scl1, high impedance
max4895e vga port protector _______________________________________________________________________________________ 7 charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1500 high- voltage dc source device under test figure 1a. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amps figure 1b. human body current waveform charge-current- limit resistor discharge resistance storage capacitor c s 150pf r c 50m to 100m r d 330 high- voltage dc source device under test figure 1c. iec 61000-4-2 esd test model t r = 0.7ns to 1ns 30ns 60ns t 100% 90% 10% i peak i figure 1d. iec 61000-4-2 esd generator current waveform human body model (hbm) figure 1a shows the human body model, and figure 1b shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of interest that is then discharged into the test device through a 1.5k resistor. iec 61000-4-2 the iec 61000-4-2 standard covers esd testing and performance of finished equipment. however, it does not specifically refer to integrated circuits. the max4895e assists in designing equipment to meet iec 61000-4-2 without the need for additional esd-protec- tion components. the major difference between tests done using the human body model and iec 61000-4-2 is higher peak current in iec 61000-4-2 because series resistance is lower in the iec 61000-4-2 model. hence, the esd with- stand voltage measured to iec 61000-4-2 is generally lower than that measured using the human body model. figure 1c shows the iec 61000-4-2 model, and figure 1d shows the current waveform for iec 61000-4-2 esd contact discharge test. chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 tqfn-ep t1633+4 21-0136 90-0031
max4895e vga port protector maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/09 initial release 1 6/10 deleted the top mark column from the ordering information 1
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